The primary role of packaging in semiconductor electronic applications or microelectronic assemblies is to protect and preserve the performance of the semiconductor device from electrical, mechanical, and chemical corruption or impairment. The traditional packaging technology that has supported device protection and performance requirements include such structures as the dual in-line package and the quad flat package. More than 97 percent of current commercial semiconductor products presently use these formats. Typically in these applications, an integrated circuit chip is electronically connected to the package via wire bonding. The dual in-line package uses pins to connect the package chip to the electronic system, and these pins are inserted into a printed circuit board or socket assembly. Leads of the quad flat package, however, are solder mounted to the surface of the printed circuit board rather than being inserted into the board as is the case with the dual in-line package. This system of surface mount technology can support many more packages to board leads than can the dual in-line package. However, at a certain point, currently at approximately 250 leads, the increased difficulty in manufacturing the quad flat package format reaches a practical limit to further extension of higher lead counts. Accordingly, the commercial industry is moving away from these types of packages and to alternative package arrangements, particularly using flip chip packages.
A flip chip microelectronic assembly includes a direct electrical connection of face down (that is, “flipped”) electronic components onto substrates, such as ceramic substrates, circuit boards, or carriers using conductive bump bond pads of the chip. Flip chip technology is quickly replacing older wire bonding technology that uses face up chips with the wire connected to each pad on the chip.
The flip chip components used in flip chip microelectronic assemblies are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and MEM devices are also being used in flip chip form. Flip chips are also known as “direct chip attach,” because the chip is directly attached to the substrate, board, or carrier by the conductive bumps.
The use of flip chip packaging has dramatically grown as a result of the flip chips advantages in size, performance and flexibility over other packaging methods and from the widening availability of flip chip materials, equipment and services. In some cases, the elimination of old technology packages and bond wires may reduce the substrate or board area needed to secure the device by up to 25 percent, and may require far less height. Further, the weight of the flip chip can be less than 5 percent of the old technology package devices.
Flip chips are advantageous because of their high-speed electrical performance when compared to other assembly methods. Eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path resulting in a high speed off-chip interconnection.
Flip chips also provide the greatest input/output connection flexibility. Wire bond connections are generally limited to the perimeter of the chip or die, driving the die sizes up as a number of connections have increased over the years. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Further, flip chips can be stacked in 3-D geometries over other flip chips or other components.
Flip chips also provided the most rugged mechanical interconnection. Flip chips when underfilled with an adhesive such as an epoxy, can withstand the most rugged durability testing. In addition to providing the most rugged mechanical interconnection, flip chips can be the lowest cost interconnection for high-volume automated production.
The bumps of the flip chip assembly serve several functions. The bumps provided an electrical conductive path from the chip (or die) to the substrate on which the chip is mounted. A thermally conductive path is also provided by the bumps to carry heat from the chip to the substrate. The bumps also provided part of the mechanical mounting of the chip to the substrate. A spacer is provided by the bumps that prevents electrical contact between the chip and the substrate connectors. Finally, the bumps act as a short lead to relieve mechanical strain between the chip and the substrate.
Flip chips can be combined with a variety of packages. The ball grid array is one particular package which has gained significant popularity for use with the flip chip. The ball grid array package construction is significantly different from conventional leaded packages in several ways. Typically the ball grid array uses a resin based organic substrate (first substrate) onto which the flip chip die and solder balls are attached. The substrate incorporates metalized trace routing for connection from the die to a second substrate, such as a system board. The connection made to the second substrate is through solder balls on the underside of the first substrate. Ball grid array packages provided numerous advantages over conventional leaded packages such as: improved electrical performance due to shorter distances between the chip and the solder balls; improved thermal performance by use of thermal vias or heat dissipation through power and ground planes incorporated into the second substrate (e.g., main PC board); using less real estate on the underlying system board or second substrate; significantly reducing handling related lead damage due to use of solder balls instead of metal leads; and when the ball grid array is reflow attached to boards, the solder balls self align leading to higher manufacturing yields.
Despite all of these advantages, these microelectronic assemblies are very delicate structures, the design of which and manufacturing creates difficult and unique technical problems. Continuous efforts by those working in the art are being undertaken to improve the performance, reliability and useful life of microelectronic assemblies, particularly those using flip chips. The following is a description of some of the problems facing those skilled in the art.
Typically a flip chip will be mounted and electrically connected to a supporting substrate such as a ball grid array. The supporting substrate may be secured to a printed circuit board. The flip chip can generate a considerable amount of heat during operation which may range from about 25 to 100 watts concentrated in the area the chip which usually ranges from 1 to 4 cubic centimeters. Those working in the art are constantly seeking ways to control and manage this concentrated heat generation to avoid failure of the microelectronic device due to overheating.
Failure to manage the heat generated by the flip chip may be very costly. The heat generated from the flip chip during operation may cause the chip dimensions to change and may result in damage to signals generated by the chip. Furthermore, thermal expansion may cause the chip to curve, bend or crack. These distortions in the chip may result in damage to the electrical connections between the chip and the substrate.
Furthermore, the substrate onto which the flip chip may be mounted can be a single layer structure, or the substrate may comprise two or many more layers of materials. Often these materials tend to be quite diverse in their composition and structure. The coefficient of thermal expansion for these different layers may be considerably different and may result in uncontrolled bending or thermal induced substrate surface distortions. Such distortions can cause failure of the flip chip or other components of the substrate.
In addition to chip warpage (or warping) due to thermal effects, chip or substrate warpage may be caused by other steps of the manufacturing process. For example, chip warpage may occur as a consequence of the chip underfill process. Typically, an adhesive underfill is applied between the opposing faces of the chip and the underlying substrate to secure the chip to the substrate and to secure the electrical connections, usually solder joints, between the chip and the substrate. When the adhesive underfill is cured or hardened, the cured adhesive tends to shrink placing the solder joints in a compressed state, and often the shrinking adhesive causes warpage of the substrate.
The use of underfills and ball grid array (BGA) have played a significant factor in the viability of flip chips. As indicated earlier, a BGA is a high-density integrated circuit surface mount package with an area array of conductive bumps or solder balls for interconnection to a substrate. The coefficient of thermal expansion (CTE) of silicon is about 2.6 ppm/° C., and that of glass fiber reinforced printed wiring board or printed circuit board (PCB) is about 17 ppm/° C. The ball grid array (BGA) substrate is the intermediary between the silicon and the PCB with a CTE of 6 ppm/° C. for ceramic BGA, and 17 ppm/° C. for organic BGA. The larger CTE difference between the BGA and the silicon chip puts a significant sheer stress on the flip chip interconnection. The use of underfills between the front side of the chip and the top side of the printed circuit board BGA substrate distributes the stress over the entire surface of the integrated circuit chip, thus reducing the stress on the flip chip solder joints. The impact of this CTE mismatch is that the entire assembly flexes during thermal cycling to distribute away the stresses from the solder balls.
FIG. 1 illustrates a flip chip BGA assembly that includes a semiconductor integrated circuit chip 10 having a top face 12 that is positioned face down towards a top face 13 of an underlying first substrate 14. A first set of electrically conductive bumps, preferably solder bumps, 16 connect the integrated circuit chip 10 to the first substrate 14. A bottom face 18 of the first substrate 14 has a second set of electrically conductive bumps, preferably solder bumps, 20 that are connected to contact pads (not shown) on a top first surface 24 of an underlying second substrate 22. As will be appreciated from FIG. 1, the second set of electrically conductive bumps or solder bumps 20 may be fully arrayed across the entire surface of the bottom face 18 of the first substrate. The second substrate 22 may be a printed wiring board (also known as a printed circuit board). Typically an underfill 21 is provided between the top face 12 of the integrated flip chip 10 and the top face 13 of the first substrate 14. The underfill encapsulant 21 also helps to reduce the effect of the global thermal expansion mismatch between the flip chip 10 and the first substrate 14 of the BGA. The underfill typically has a low thermal coefficient of expansion which helps to reduce the thermal expansion mismatch between the flip chip 10, solder bumps 16, and the first substrate 14. Other advantages of the underfill encapsulant are that it protects the chip from moisture, ionic contaminants, radiation, and hostile operating environments such as thermal and mechanical conditions, shock, and vibration. The underfill may also act as a heat sink, providing a major heat path between the flip chip 10 and the underlying first substrate 14 of the BGA. As shown in FIG. 1, the first set of electrically conductive bumps or solder bumps 16 are positioned across substantially the entire top face 12 of the integrated circuit chip and is thus known as a fully arrayed integrated circuit flip chip. In certain situations, fully arrayed integrated circuit chips are disadvantageous because they utilize more package substrate layers needed for input/output trace routing and have an associated increased substrate cost, as well as assembly costs.
FIG. 2 illustrates a flip chip BGA assembly similar to that shown in FIG. 1, however, the first set of electrically conductive bumps or solder bumps 16 are not fully arrayed, but are positioned along the periphery 28 of the integrated circuit chip 10. Because the flip chip is bumped along the periphery 28, a gap 30 in the positioning of the bumps 16 is provided along the sides and center of the flip chip. Likewise, the second set of electrically conductive bumps or solder bumps 20 are secured to the periphery 32 of the bottom face 18 of the first substrate 14. Similarly, a gap 34 in the positioning of the bumps 20 is provided along the sides and center of the bottom face 18 of the first substrate 14. Periphery mounted bump flip chips are much less expensive to manufacture than fully arrayed flip chip microelectronic assemblies. However, during the flip chip mounting process, the electrically conductive bumps or solder bumps 16 are reflown at elevated temperatures (above room temperature) to reflow the solder and mechanically attach the flip chip to contact pads (not shown) on the top face 13 of the first substrate 14. Further, typically an underfill is flown into the cavity between the top face 12 of the integrated circuit chip 10 and the top face 13 of the first substrate 14. The underfill material is typically cured at elevated temperatures (above room temperature). The flip chip mounting process and the underfill curing process each induce thermal-mechanical stresses in the bump joints due to the mismatch between the thermal expansion coefficient of the integrated circuit chip 10 and the first substrate 14. Still further, during operation of the integrated circuit chip, and thermal cycling, substantial thermal-mechanical stresses may be applied to the solder bumps 16 of the flip chip. Thus, it would be desirable to provide a method of flip chip mounting and underfill curing that reduced or accommodated thermal-mechanical stresses ordinarily associated with such processes. Furthermore, it would be desirable to provide a microelectronic assembly and method of manufacturing the same that would reduce or accommodate thermo-mechanical stresses induced during thermal cycling under normal operation of the microelectronic assembly.
The present invention satisfies an existing need and provides improvements, and alternatives to the prior.